Multi-well selenium device and method for fabrication thereof

ABSTRACT

Provided is a field shaping multi-well detector and method of fabrication thereof. The detector is configured by depositing a pixel electrode on a substrate, depositing a first dielectric layer, depositing a first conductive grid electrode layer on the first dielectric layer, depositing a second dielectric layer on the first conductive grid electrode layer, depositing a second conductive grid electrode layer on the second dielectric layer, depositing a third dielectric layer on the second conductive grid electrode layer, depositing an etch mask on the third dielectric layer. Two pillars are formed by etching the third dielectric layer, the second conductive grid electrode layer, the second dielectric layer, the first conductive grid electrode layer, and the first dielectric layer. A well between the two pillars is formed by etching to the pixel electrode, without etching the pixel electrode, and the well is filled with a-Se.

PRIORITY

This application claims priority to U.S. Provisional Patent ApplicationNo. 62/275,919 filed with the U.S. Patent and Trademark Office on Jan.7, 2016, the entire contents of which is incorporated herein byreference.

GOVERNMENT SUPPORT

This invention was made with government support under grant number 1R21EB01952601A 1 awarded by the National Institute of Health. Thegovernment has certain rights in the invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates generally to the field of solid-stateradiation imaging detectors and, in particular, to amorphous seleniumradiation detectors having a field-shaping multi-well detectorstructure.

2. Description of the Related Art

Soon after the Nobel Prize winning invention of the gas-filledmulti-wire proportional chamber by Charpak in 1968, and parallel todevelopments in microelectronics, micro-pattern gaseous detectors weredeveloped for improved position resolution. However, the range ofradiation induced photoelectrons is micrometer-to-millimeter, with gassolid-state detectors having three orders of magnitude shorterphotoelectron range due to their much higher density. Thus, solid-statedetectors yield images with substantially higher spatial/temporalresolution. Disordered solids, which are easier and less expensive todevelop than single crystalline solids, have not been utilized asphoton-counting mode detection media because of low carrier mobility andtransit-time-limited photo response.

Amorphous selenium (a-Se), which was previously developed forphotocopying machines, has been commercially revived as a direct x-rayphotoconductor for flat-panel detectors (FPD) because a-Se has a highx-ray sensitivity and can be uniformly evaporated over large area as athick film.

A non-ohmic effect in disordered solids may occur in the presence of astrong field with the transport mechanism shifted from localized statesinto extended states where the mobility can be increased by 100 to 1000times. Such hot carriers in extended states with mobilities near amobility edge can gain energy faster than they lose energy to phonons.Thus, avalanche due to impact ionization is possible [2], e.g., hotholes in a-Se [3-5], in contrast to hot electrons in amorphous silicon[6]. Continuous and stable avalanche multiplication has been shown ina-Se, a feature that enabled the development of an optical camera withhigher sensitivity than the human eye, i.e., 11× at aperture F8, or 100times more sensitive than a CCD camera) [7]. For high-energy penetratingradiation, the challenge is that avalanche-mode selenium cannot be thebulk medium because avalanche layers cannot be very thick (<25 μm) and auniform avalanche field in the bulk causes depth-dependent gainvariations.

Positron emission tomography (PET) is a nuclear medical imaging modalitythat produces three-dimensional (3D) images to see functional processesin human body. PET is most commonly used in clinical oncology fordetecting cancer and for clinical diagnosis of heart problems and/orbrain disorders. After being introduced into the body, positron-emittingradionuclides decay with each annihilation, emitting two photons indiametrically opposing directions. Time of flight (TOF) measurements maybe utilized to measure the time for the electromagnetic wave to travel adistance through a medium. A TOF PET system detects the photons, anduses TOF information to determine if two registered photons are in timecoincidence, i.e., belong to a same positron annihilation event. The TOFPET system uses the arrival time difference to localize eachannihilation event. Without the TOF localization data, computationallyexpensive iterative reconstruction algorithms are used to estimate the3D distribution of events that provide the best match with the measuredprojection data.

Localization accuracy Δx of a TOF PET system is determined bytime-resolution Δt of the radiation detector according to Equation (1):Δx=cΔt/2,   (1)where c is the speed of light. A goal of a TOF PET detector is Δt<10picoseconds (ps). However, this goals has not been realized.

Existing systems utilize expensive photomultiplier tubes (PMTs) that arebased on the complicated plano-concave photocathode, yet can onlyachieve Δt of ˜500 ps. Silicon photomultipliers (SiPMs), which are basedon Geiger mode operating avalanche photodiodes, are rapidly developing.SiPMs have achieved Δt better than PMTs, i.e., with SiPM achieving a Δtof ˜100 ps. However, SiPMs suffer from poor photon detection efficiency,optical crosstalk, small area, poor uniformity, and high cost.

A direct conversion a-Se FPD with separate absorption and avalanche gainregions has been proposed [8,9] and theoretical imaging performance hasbeen analyzed [4]. It has been shown that a separate localized avalanchemultiplication region minimizes gain variation compared to bulkavalanche, i.e., avalanche in entire volume of a-Se [10]. However, suchdirect conversion a-Se FPD has not been realized due to formation offield hot-spots, where the applied electric field (F) exceeds 150 V/μm,which lead to irreversible material breakdown.

Limitations of direct conversion a-Se FPDs include degradation oflow-dose imaging performance due to electronic noise since the energyrequired to generate an electron-hole pair in a-Se is 50 eV at 10V/micron. Although other photoconductive materials with higherconversion have been investigated, direct conversion a-Se FPDs remainfar from commercialization due to charge trapping and manufacturingissues. Improved conversion of a-Se is possible by increasing theelectric field above 30 V/micron, i.e., 30,000 V on a 1000 micron layer.However, this electric field increase is extremely challenging forreliable detector construction and operation, and is impractical.

Amorphous solids, i.e., non-crystalline solids with disorder, have beenruled out as viable radiation imaging detectors in a photon-countingmode because of low temporal resolution due to low carrier mobilitiesand transit-time limited pulse response, and low conversion gain of highenergy radiation to electric charge. A direct conversion a-Se layer withseparate absorption and avalanche region has been suggested, butsignificant obstacles prevent practical implementation of a directconversion a-Se layer with separate absorption and avalanche regions.

Unipolar solid-state detectors with a Frisch grid have been proposed.[11-13] However, such detector structures are not practical for directconversion avalanche gain because the highest electric field in the welldevelops at the interface between the semiconductor and the pixelelectrode, resulting in a high dark current due to large chargeinjection and potentially irreversible damage to the detector.

A unipolar time-differential (UTD) solid-state detector has beenfabricated using a high granularity micropattem multi-well structure,i.e., a multi-well solid-state detector (MWSD), as shown in FIG. 1,which is a cross-section of a MWSD obtained by a scanning electronmicroscope (SEM) [12]. As shown in FIG. 1, a common electrode 110 isprovided at an upper portion thereof and a substrate 160 is provided atan opposite lower portion. A pixel electrode 130 is formed on an uppersurface of the substrate 160 as a collector, and a plurality ofinsulators are formed on an upper surface of the pixel electrode 130,with a shield 120 formed on top of each insulator 150 of the pluralityof insulator. A plurality of wells 140, 142 are provided betweenrespective insulators of the plurality of insulator.

Time-of-flight experimental results show substantial improvement in thedetector's time resolution due to UTD charge sensing. Also, an ultimatephysical limit in signal risetime, as set by the spreading of thephoto-induced carrier packet, was achieved. [12,13,15-17] However,conventional systems do not etch dielectric at the bottom of wells, norare grid electrodes encapsulated with dielectric layers provide on eachside thereof.

Other amorphous selenium multi-well avalanche detectors fabricationmethods have been proposed for nano-electrode multi-well high-gainavalanche rushing photoconductor and a field-shaping multi-wellavalanche detector. [15, 16] However, these methods require alignment,i.e., alignment during lithography, for encapsulating the gridelectrodes with insulator/dielectric while removing theinsulator/dielectric at the bottom of the wells.

SUMMARY OF THE INVENTION

To overcome shortcomings of conventional systems, a multi-well seleniumdetector provided herein and a method for the fabrication of same thateliminates the required alignment and encapsulates grid electrodes withthe insulator/dielectric.

Accordingly, aspects of the present invention address the above problemsand disadvantages and provide the advantages described below. An aspectof the present invention provides practical detector structures withoutfield hot-spots to realize direct conversion avalanche a-Se.

An aspect of the present disclosure provides a method of fabricating amulti-well amorphous selenium (a-Se) detector, comprising depositing apixel electrode on a substrate; depositing a first dielectric layer;depositing a first conductive grid electrode layer on the firstdielectric layer; depositing a second dielectric layer on the firstconductive grid electrode layer; depositing a second conductive gridelectrode layer on the second dielectric layer; depositing a thirddielectric layer on the second conductive grid electrode layer;depositing an etch mask on the third dielectric layer; performing afirst etching to form at least two pillars with at least one welltherebetween; depositing an oxide dielectric layer on the at least twopillars and on a bottom of the at least one well; and performing asecond etching to remove the oxide dielectric layer from the bottom ofthe at least one well.

Another aspect of the present disclosure provides a nanopattern,multi-well, solid-state a-Se radiation detector comprising asemiconductor, a pixel electrode, a first dielectric layer, a seconddielectric layer, a third dielectric layer, a first conductive gridelectrode layer, and a second conductive grid electrode layer. The pixelelectrode is deposited on the substrate, the first conductive gridelectrode layer is deposited on the first dielectric layer, the seconddielectric layer is deposited on the first conductive grid electrodelayer, the second conductive grid electrode layer is deposited on thesecond dielectric layer, the third dielectric layer is deposited on thesecond conductive grid electrode layer, an etch mask is deposited on thethird dielectric layer, a first etching forms at least two pillars withat least one well therebetween, an oxide dielectric layer is depositedon the at least two pillars and on a bottom of the at least one well,and a second etching removes the oxide dielectric layer from the bottomof the at least one well.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and advantages of certainembodiments of the present invention will be more apparent from thefollowing detailed description taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is an SEM cross-section of a conventional micro well solid-statedetector;

FIGS. 2(a)-2(l) illustrate a method to fabricate a multi-well substratewith encapsulated pillars according to an embodiment of the presentdisclosure;

FIG. 3(a) is an exploded view of a pillar array having encapsulated gridelectrodes, formed on an array of pixel electrodes according to anembodiment of the present disclosure;

FIG. 3(b) is an assembled view of the pillar array of FIG. 3(a);

FIG. 4 is a top view of a conventional device;

FIG. 5(a) is a top view of a linear array of micro-strip grid electrodesover a multi-pixel substrate according to an embodiment of the presentdisclosure;

FIG. 5(b) is a profile view of the assembled pillar array of FIG. 5(a);

FIG. 6 is a top view of another embodiment of the two-dimensional arrayof micro-mesh grid electrodes using hexagonal/honeycomb geometry over amulti-pixel substrate according to the present disclosure; and

FIGS. 7(a)-7(d) illustrate fabrication of a multi-well structure withtwo grid electrodes according to an embodiment of the presentdisclosure.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The following detailed description of certain embodiments of the presentinvention will be made with reference to the accompanying drawings. Indescribing the invention, explanation about related functions orconstructions known in the art are omitted for the sake of clearness inunderstanding the concept of the invention, to avoid obscuring theinvention with unnecessary detail.

Disclosed herein is a solid-state avalanche radiation detector, and amethod for constructing same, using amorphous material as thephotoconductive layer without field hot-spots, to provide a directconversion avalanche a-Se. The solid-state avalanche radiation detectoris based on field-shaping by localizing the high-field avalanche regionbetween two low-field regions, improving on the devices of Sauli, Lee,and Goldan. [9, 11, 14-16]

The present disclosure optimizes the solid-state detector structure toprovide stable avalanche multiplication gain in direct conversionamorphous selenium radiation detectors. The detector structure isreferred to as a field-shaping multi-well avalanche detector (SWAD) thatprovides a practical manner to achieve stable avalanche in large areadirect radiation detectors, by varying thickness of a low-fieldinteraction region to stop high-energy radiation and optimizing thehigh-field multi-well detection region for avalanche multiplication.

Stable avalanche multiplication gain is achieved by eliminating fieldhot-spots using high-density avalanche wells with insulated walls, withfield-shaping within each well.

The high-density insulated wells and field-shaping eliminates formationof field hot-spots in the avalanche region and eliminates high fields atthe metal-semiconductor interface. The electric field at themetal-semiconductor interface is one order-of-magnitude lower than apeak value where avalanche occurs. The field-shaping electrodes,high-density insulated wells and field-shaping provide a semi-Gaussianfield distribution inside each well.

FIGS. 2(a)-2(l) illustrate a method to fabricate a multi-well substratewith encapsulated pillars according to an embodiment of the presentdisclosure. FIGS. 2(a)-2(l) illustrate relevant sequential steps in thefabrication. For conciseness, FIGS. 2(a)-2(l) illustrate only two gridlayers, repetition of which allows for depositing of more than twoinsulating dielectric layers and conductive grid electrodes.

FIG. 2(a) illustrates conductive pixel electrode 230 being patterned ona substrate 260 by photolithography. The substrate 260 is preferablyglass, e.g., quartz, soda lime, fused silica, or silicon. Alternatively,a thin-film transistor (TFT) substrate or a complementary metal-oxidesemiconductor (CMOS) substrate can be utilized with a previouslypatterned pixel electrode. The pixel electrode 230 is configured tocollect generated electronic charges, and is preferably formed ofconductive materials that include Aluminum (Al), Chromium (Cr), Tungsten(W), Indium tin oxide (ITO), and Zinc oxide (ZnO).

FIG. 2(b) illustrates a first dielectric layer 241, i.e., insulatinglayer, deposited on the substrate 260. Dielectric materials are poorconductors of electric current, and deposition is preferably performedvia one of physical vapor deposition (PVD), spin casting,plasma-enhanced chemical vapor deposition (PECVD), and atomic layerdeposition (ALD). The PVD can include thermal evaporation, electron-beamevaporation, or sputtering. The first dielectric layer 241 is formedfrom non-conductive or very low-conductivity materials, e.g., polyimide(PI), Silicon Oxide (SiO), Silicon Nitride (SiN), and Aluminum Oxide(AlO).

FIG. 2(c) illustrates a first conductive grid electrode layer, i.e.,grid-1, deposited on the first dielectric layer 241. FIG. 2(d)illustrates second dielectric layer 242 deposited on first conductivegrid electrode layer 251. FIG. 2(e) illustrates a second conductive gridelectrode layer 252, i.e., grid-2, deposited on the second dielectriclayer 242. FIG. 2(f) illustrates a third dielectric layer 243 depositedon the second conductive grid electrode layer 252.

As shown in FIG. 2(g), after depositing the third conductive dielectriclayer 243 on the second conductive grid electrode layer 252, a masklayer 280 is deposited on the third dielectric layer 243, as an etchmask. The mask layer 280 is a metal, an organic photoresist or othermaterial having high etch resistivity. FIG. 2(h) illustrates the masklayer 280 being patterned using optical contact photolithography,optical lithography, e.g., stepper lithography, or electron beamlithography (EBL).

FIG. 2(i) illustrates results of anisotropic etching that preservespatterning. The anisotropic etching continues through the layereddielectrics and grids until the pixel electrode 230 is reached, and doesnot etch the pixel electrode 230. Dry etching is preferably used forboth dielectrics and grid electrodes.

Dry etching may be performed using reactive ion etching (RIE) or deepRIE. Anisotropic etching of organic polymer dielectric is preferablyperformed with a deep RIE tool using an inductively charged plasma (ICP)etch system at low pressure and low temperature. Anisotropic etching ofoxide dielectrics, such as SiO, is preferably performed usingfluorinated anisotropic etching where each dry etch sequence is followedby a secondary plasma deposition that furnishes a layer of fluorocarbonpolymer passivation on the sidewalls. Other anisotropic etchingtechniques may be utilized as long as the oxide is only verticallyetched at well bottoms without sidewall etching, thereby preservingoxide at the sidewalls during the etch to encapsulate the gridelectrodes inside the wells.

FIG. 2(j) illustrates deposit of a dielectric oxide dielectric layer285, e.g., SiO, AlO, that conformally encapsulates pillars 271, 272 andwell 290. Conformal oxide deposition methods include atomic layerdeposition (ALD) and silane-based PECVD. Liquid tetraethoxysilane (TEOS)can be used as a source of Si instead of silane gas (TEOS-PECVD).

FIG. 2(k) illustrates anisotropic etching of an upper surface of theremaining mask layer 280, and the oxide at the bottom of the well, usingdry RIE. The anisotropic etching removes the encapsulation betweenpillars 271, 272 at the bottom of the well 290. Anisotropic etching ofoxide dielectrics, such as SiO, maybe done using fluorinated anisotropicetching where each dry etch sequence is followed by a secondary plasmadeposition that furnishes a very thin fluorocarbon polymer passivationon the sidewalls.

FIG. 2(l) illustrates removal of the etch mask by either dry or wetetching, thereby forming the multi-well substrate having at least twoencapsulated grid electrodes, formed on substrate 260. The anisotropicetching yields substantially vertical sidewalls, and forms at least twopillars 271, 272, each of width W (FIG. 2(h)), with gap G therebetween.

FIG. 3(a) is an exploded view of a pillar array having encapsulated gridelectrodes, formed on an array of pixel electrodes according to anembodiment of the present disclosure.

FIG. 3(b) is an assembled view of the pillar array of FIG. 3(a). FIG.3(c) is a profile view of the assembled pillar array of FIG. 3(a).

FIGS. 3(a) to 3(c) illustrate a device configured for scanning controland multiple busses for output from the pixel electrode array to animager substrate with TFT or CMOS readout electronics, or the like. Asshown in FIGS. 3(a) and 3(b), a multi-well structure 340 is formed ontop of a substrate 360. An a-Se layer 320 fills wells of the multi-wellstructure 340, up to a common electrode 310. The a-Se layer 320 is ann-i-p or p-i-n layer with the p- or similar layer as the first layerdeposited over the substrate, i.e., the multi-well substrate, followedby the i-layer, then the n- or similar layer, followed by the highvoltage electrode. Once the multi-well structure is formed on thesubstrate, the amorphous selenium photoconductor is deposited over themulti-well substrate. The selenium deposition may include the p-i-nprocess where a p-like electron-blocking layer is first deposited overthe multi-well substrate. The intrinsic stabilized selenium is thenevaporated to form a bulk semiconductor layer. An n-like, i.e., n-type,hole-blocking layer is then deposited, and a conductive high-voltage(HV) electrode is then deposited. For optical light detection, theconductive HV electrode is transparent or semi-transparent. For example,ITO or ZnO are conductive layers that can also be optimized for highlight transparency.

As shown in FIGS. 2(k), 2(l), 3(a), and 3(b) the oxide at the bottom ofeach of the wells is etched away.

FIG. 4 is a top view of a conventional device. As shown in FIG. 4, inconventional devices, each well 490 a-490 p corresponds to no more thanone pixel 431-426, each well is square in shape, each well is surroundedby the pixel boundary in both X and Y dimensions, and wells must bealigned to a central axis of the pixel electrode.

FIG. 5(a) is a top view of a linear array of micro-strip grid electrodesover a multi-pixel substrate according to an embodiment of the presentdisclosure. FIG. 5(b) is a profile view of the assembled pillar array ofFIG. 5(a). Comparison of FIG. 4 to FIGS. 5(a) and 5(b) shows that thepresent disclosure allows each well 590 a-590 i to be shared by many,i.e., at least two, pixel electrodes 531, 532; that each well 590 a-590i is not restricted by the shape of the pixel electrode and can extendacross pixel boundaries; and that wells 590 a-590 i are formed frommicro-strip grid of electrodes 550 and dielectric 540. As shown in FIG.5(b), the electrodes include a top grid 550 a and a bottom grid 550 b. Alinear array of micro-strip grid electrodes is provided over amulti-pixel substrate with wells that do not need to be aligned to anypixel electrode, provides overlapping grid electrodes that areself-aligned to each other.

FIG. 6 is a top view of another embodiment of the two-dimensional arrayof micro-mesh grid electrodes using hexagonal/honeycomb geometry over amulti-pixel substrate according to the present disclosure. As shown inFIG. 6, pixels 631-634 form the multi-pixel substrate, with a pluralityof wells 690 a, 690 b, 690 c, 690 d . . . , with micro-mesh gridelectrodes inside the dielectric layer. Comparison of FIG. 4 to FIG. 6shows that the present disclosure allows some wells to be shared bymany, i.e., at least two, pixel electrodes; that each well is notrestricted by the shape of the pixel electrode and can extend acrosspixel boundaries; and also that wells can be formed from micro-mesh gridelectrodes, in a honeycomb shape.

FIGS. 7(a)-7(d) illustrate fabrication of a multi-well structure withtwo grid electrodes according to an embodiment of the presentdisclosure. The multi-well structure of FIGS. 7(a)-7(d) was fabricatedover glass substrates by:

-   -   depositing the pixel electrode 230 on the substrate 260 via        Aluminum sputtering;    -   patterning the pixel electrode 230 using contact        photolithography;    -   depositing the first dielectric layer 241 via spin-casting        polyimide;    -   curing the polyimide;    -   depositing the first conductive grid electrode layer 251 on the        first dielectric layer 241 via Tungsten sputtering;    -   depositing the second dielectric layer 242 on the first        conductive grid electrode layer 251 via sputtering Tungsten;    -   depositing the third dielectric layer 243 on the second        conductive grid electrode layer 252 via spin-casting polyimide;    -   curing the polyimide;    -   depositing the etch mask layer 280 on the third dielectric layer        243 via sputtering Cr;    -   patterning the etch mask layer 280 using contact        photolithography;    -   Cr etching using an RIE system; and    -   etching the well until the pixel electrode is reached.

The etching of the well until the pixel electrode is preferablyperformed by: anisotropically etching the third dielectric layer 243using oxygen plasma (O2 plasma) inside an ICP deep RIE system;

-   -   etching the second conductive grid electrode layer 252 via dry        etching of W with SF6 plasma;    -   anisotropically etching the second dielectric layer using O2        plasma inside an ICP deep RIE system;    -   etching the first conductive grid electrode layer via dry        etching of W with SFG plasma; and    -   anisotropically etching the first dielectric layer 241 using O2        plasma inside an ICP deep RIE system.

After etching the wells, SiO2 is conformally deposited using aTEOS-PECVD system, with FIG. 7(a) showing an ideal structure afteretching the well, encapsulating the pillars and wells conformally withan oxide dielectric layer. FIG. 7(b) is an SEM cross-section showing thestructure fabricated using the process described herein. FIG. 7(b) andFIG. 7(d) correspond to the steps illustrated in FIG. 2(j) and FIG.2(l), respectively.

As shown in FIG. 7(c), the anisotropic etching of the oxide dielectriclayer removes only the oxide from the bottom of the wells and top of themask, without etching the oxide at the sidewalls. Leaving the oxide onthe sidewalls ensures complete encapsulation of the grid electrodes bydielectric layers on all sides. The anisotropic etch of SiO2 ispreferably performed using fluorinated anisotropic etching, with eachdry etch sequence followed by a secondary plasma deposition thatfurnishes a very thin flour-carbon polymer passivation on the sidewalls.

The Cr mask is preferably etched using wet etching. FIG. 7(d) is an SEMcross-section showing preferred anisotropic oxide etching where the SiO2remained intact, without etching the sidewalls.

As shown in FIG. 7(b) and FIG. 7(d), the anisotropic, i.e., vertical,removal of oxides at the bottom of well 290 and at the top of the mask,with the oxide on the sidewalls of the pillars not being etched, allowsfor complete encapsulation of the grid electrodes inside the dielectriclayers.

Provided is a nanopattern, multi-well, solid-state a-Se radiationdetector that includes a semiconductor, a pixel electrode, at leastthree dielectric layers, and at least two conductive grid electrodelayers. The pixel electrode is deposited adjacent to the substrate and afirst conductive grid electrode layer of the at least two conductivegrid electrode layers is deposited on a first dielectric layer of the atleast three dielectric layers. A second dielectric layer of the at leastthree dielectric layers is deposited on the first conductive gridelectrode layer. A second conductive grid electrode layer of the atleast two conductive grid electrode layers is deposited on the seconddielectric layer. A third dielectric layer of the at least threedielectric layers is deposited on the second conductive grid electrodelayer, and an etch mask is deposited on the third dielectric layer. Afirst etching forms at least two pillars with at least one welltherebetween, an oxide dielectric layer is deposited on the at least twopillars and on a bottom of the at least one well, and a second etchingremoves the oxide dielectric layer from the bottom of the at least onewell. More than two conductive grid electrode layers may also beutilized. If, e.g., three conductive grid electrode layers are utilized,a third dielectric layer is formed on the second conductive gridelectrode layer, a third conductive grid electrode layer is formed onthe third dielectric layer, and a fourth dielectric layer is formed onthe third conductive grid electrode layer, thereby forming an n+1dielectric layer on an nth conductive grid electrode layer, with theetch mask being deposited on the n+1 dielectric layer. The first etchingis then performed to form at least two pillars with at least one welltherebetween, as described above.

The apparatus provided by the present disclosure provides a UTD chargesensing, which enables operating the detector at its theoretical limitof charge diffusion, improves in an avalanche-mode by more than threeorders-of-magnitude.

While the invention has been shown and described with reference tocertain aspects thereof, it will be understood by those skilled in theart that various changes in form and details may be made therein withoutdeparting from the spirit and scope of the present invention as definedby the appended claims and equivalents thereof.

REFERENCES

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[2] N. F. Mott; Conduction in non-crystalline systems. VII. Non-ohmicbehavior and switching. Phil. Mag., 24(190): 911-934, 1971.

[3] G. Juska and K. Arlauskas; Impact ionization and mobilities ofcharge carriers at high electric fields in amorphous selenium. Phys.Stat. Sol. (a), 59(1): 389-393, 1980.

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What is claimed is:
 1. A nanopattern, multi-well, solid-state a-Seradiation detector comprising: a semiconductor; a pixel electrode; atleast three dielectric layers; and at least two conductive gridelectrode layers, wherein the pixel electrode is deposited adjacent to asubstrate, wherein a first conductive grid electrode layer of the atleast two conductive grid electrode layers is deposited on a firstdielectric layer of the at least three dielectric layers, wherein asecond dielectric layer of the at least three dielectric layers isdeposited on the first conductive grid electrode layer, wherein a secondconductive grid electrode layer of the at least two conductive gridelectrode layers is deposited on the second dielectric layer, wherein athird dielectric layer of the at least three dielectric layers isdeposited on the second conductive grid electrode layer, wherein an etchmask is deposited on the third dielectric layer, wherein a first etchingforms at least two pillars with at least one well therebetween, whereinan oxide dielectric layer is deposited on the at least two pillars andon a bottom of the at least one well, and wherein a second etchingremoves the oxide dielectric layer from the bottom of the at least onewell.
 2. The detector of claim 1, wherein the first etching is performedfrom the third dielectric layer, to the second conductive grid electrodelayer, to the second dielectric layer, to the first conductive gridelectrode layer, to the first dielectric layer, and to the pixelelectrode, and wherein the first etching does not etch the pixelelectrode.
 3. The detector of claim 1, wherein the second etching doesnot remove the oxide dielectric layer from sides of the at least twopillars with the at least one well, and wherein the second etching doesnot etch the pixel electrode.
 4. The detector of claim 1, wherein eachof the at least two pillars includes the first conductive grid electrodelayer and the second conductive grid electrode layer, forming onopposite sides of the at least one well a pair of first conductive gridelectrode layers and a pair of second conductive grid electrode layers.5. The detector of claim 4, wherein the pair of first conductive gridelectrode layers are spaced apart from the pixel electrode by a firstdistance, wherein the pair of second conductive grid electrode layersare spaced apart from the pixel electrode by a second distance, andwherein the first distance is different from the second distance.
 6. Thedetector of claim 4, wherein the oxide dielectric layer fullyencapsulates each of the pair of first conductive grid electrode layers.7. The detector of claim 4, wherein the oxide dielectric layer fullyencapsulates each of the pair of second conductive grid electrodelayers.
 8. The detector of claim 4, wherein the pair of first conductivegrid electrode layers align with the pair of second conductive gridelectrode layers, without aligning the first conductive grid electrodelayer and the second conductive grid electrode layer before performingthe first etching.
 9. The detector of claim 1, wherein the firstconductive grid electrode layer and the second conductive grid electrodelayer are not patterned before stacking on the first dielectric layer oron the second dielectric layer, respectively.